Complete technical description of functions and characteristics for Ensemble microcontrollers and fusion processors.
E1 Series Datasheet
(v2.7) MCU with single core up to 160MHz operation, secure enclave, many standard peripherals plus optional NPU accelerator up to 46 GOPS performance, and optional graphics subsystem.
Download documentE3 Series Datasheet
(v2.7) MCU with dual cores up to 160MHz and 400MHz operation, up to very large memory, secure enclave, many peripherals plus optional AI/ML NPUs accelerators up to 250 GOPS performance.
Download documentE5 Series Datasheet
(v2.7) Fusion Processor with triple cores up to 160MHz, 400MHz, and 800MHz operation capable of running combinations of Linux and/or RTOS, large memory, secure enclave, many peripherals, and AI/ML NPUs accelerators up to 250 GOPS performance.
Download documentE7 Series Datasheet
(v2.7) Fusion Processor with quad cores up to 160MHz, 400MHz, and 800MHz operation capable of running combinations of Linux and/or RTOS, large memory, secure enclave, many peripherals, and AI/ML NPUs accelerators up to 250 GOPS performance.
Download documentEnsemble Family Errata
(v1.3) This errata lists functions in silicon revision B2 of the Ensemble Family devices that do not match the specifications in the published v2.6 datasheets. Silicon version B3 will remove these functional errata.
Download documentProduction Silicon GPIO Pin Mux Options (Gen 2)
(v1.3) This document describes the GPIO pin mux options and output grouping for the Gen 2 silicon.
Download document
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