Altium

Design Rule Verification Report

Date:		28-Feb-24
Time:		09:23:14
Elapsed Time:		00:00:02
Filename:		C:\Users\KevinBraun\Documents\Altium\Projects\120-00312_iasAdapter\120-00312-A_iasAdapter.PcbDoc

Warnings:		0
Rule Violations:		15

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=5mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=3mil) (Max=10mil) (Preferred=5mil) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=1mil) (Max=100mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Silk To Solder Mask (Clearance=4mil) (IsPad),(All)	0
Silk to Silk (Clearance=4mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Board Clearance Constraint (Gap=0mil) (All)	12
Matched Lengths(Tolerance=20mil) (InxSignalClass('xSignals_J2_J1_MatchLengthsClass'))	3
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	15

Board Clearance Constraint (Gap=0mil) (All)
Board Outline Clearance(Outline Edge): (3.778mil < 5mil) Between Board Edge And Region (0 hole(s)) Top Overlay
Board Outline Clearance(Outline Edge): (4.127mil < 5mil) Between Board Edge And Region (0 hole(s)) Top Overlay
Board Outline Clearance(Outline Edge): (4.475mil < 5mil) Between Board Edge And Region (0 hole(s)) Top Overlay
Board Outline Clearance(Outline Edge): (6mil < 15mil) Between Board Edge And Track (1085mil,1285mil)(1085mil,1616mil) on Top Overlay
Board Outline Clearance(Outline Edge): (7.001mil < 15mil) Between Board Edge And Track (1085mil,1285mil)(1186mil,1285mil) on Top Overlay
Board Outline Clearance(Outline Edge): (6mil < 15mil) Between Board Edge And Track (1085mil,1616mil)(1186mil,1616mil) on Top Overlay
Board Outline Clearance(Outline Edge): (7.753mil < 15mil) Between Board Edge And Track (1109.866mil,1285.252mil)(1162.622mil,1285.252mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (6.248mil < 15mil) Between Board Edge And Track (1109.866mil,1616.252mil)(1162.622mil,1616.252mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (6mil < 15mil) Between Board Edge And Track (1186mil,1285mil)(1186mil,1616mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (2514.5mil,1031.5mil)(2811.5mil,1031.5mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (2514.5mil,1868.5mil)(2811.5mil,1868.5mil) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 15mil) Between Board Edge And Track (2811.5mil,1031.5mil)(2811.5mil,1868.5mil) on Top Overlay

Matched Lengths(Tolerance=20mil) (InxSignalClass('xSignals_J2_J1_MatchLengthsClass'))
Matched Net Lengths: Between xSignal(MIPI_CSI_0_P_PP1) And xSignal(MIPI_CSI_1_N_PP1) Actual Length Difference against xSignal MIPI_CSI_0_P_PP1 is: 30.669mil, Length Tolerance : 20mil.
Matched Net Lengths: Between xSignal(MIPI_CSI_0_P_PP1) And xSignal(MIPI_CSI_C_N_PP1) Actual Length Difference against xSignal MIPI_CSI_0_P_PP1 is: 27.478mil, Length Tolerance : 20mil.
Matched Net Lengths: Between xSignal(MIPI_CSI_0_P_PP1) And xSignal(MIPI_CSI_C_P_PP1) Actual Length Difference against xSignal MIPI_CSI_0_P_PP1 is: 26.519mil, Length Tolerance : 20mil.